Semiconductor device and process for producing the same

ABSTRACT

A semiconductor device having a phase-change memory cell comprises an interlayer dielectric film formed of, for example, SiOF formed on a select transistor formed on a main surface of a semiconductor substrate, a chalcogenide material layer formed of, for example, GeSbTe extending on the interlayer dielectric film, and a top electrode formed on the chalcogenide material layer. A fluorine concentration in an interface between the interlayer dielectric film and the chalcogenide material layer is higher than a fluorine concentration in an interface between the chalcogenide material layer and the top electrode.

TECHNICAL FIELD

The present invention relates to semiconductor devices and a techniqueof manufacturing the same, and more particularly, it relates to atechnique effectively applied to a semiconductor device having aphase-change memory formed by using a phase-change material such aschalcogenide.

BACKGROUND ART

In mobile devices represented by mobile phones, semiconductor memoriessuch as DRAM, SRAM, and FLASH memory are used. Each of the memories hasadvantages and disadvantages, and currently, they are subjected to usedepending on the characteristics thereof.

For example, while DRAM has a large capacity, the access speed thereofis low. On the other hand, while the speed of SRAM is high, since manytransistors as much as 4 to 6 transistors are required per one cell, itis difficult to increase the degree of integration, and it is notsuitable for a large-capacity memory.

Moreover, DRAM and SRAM always require power supply to retain data(volatile). On the other hand, while FLASH memory does not require powersupply for electrical memory retention since it is non-volatile, it hasdisadvantages that the number of times of rewrite or erase is limited toabout 10⁵ times and that the rewriting speed is slower than othermemories by several digits.

If a universal memory having advantages of the DRAM, SRAM, and FLASHmemory in combination can be realized, a plurality of memories can beintegrated in one chip, and downsizing and function enhancement ofmobile phones or various mobile devices can be achieved. Furthermore, ifall semiconductor memories can be replaced, the impact is significantlylarge. Factors required for the universal memory include, for example,increasing the degree of integration (increasing capacity) to the levelof DRAM, high-speed access (write/read) to the level of SRAM,non-volatility like FLASH memory, and low-power consumption that canwithstand small battery drive, etc.

Among next-generation non-volatile memories called universal memories,what is currently attracting attention the most is a phase-changememory. The phase-change memory uses a chalcogenide material that isused in optical disks such as CD-RW and DVD and similarly stores data bythe difference between a crystalline state and an amorphous state. Thedifference between the phase-change memory and the optical disk residesin the writing/reading method. The optical disk utilizes transmissionand reflection of light typified by laser; on the other hand, in thephase-change memory, write is performed by Joule heat generated by acurrent, and a signal is read by the difference of resistance valuescaused by phase change.

Regarding a phase-change memory cell, there is a description inTechnical Digest of International Electron Device Meeting, 2001, p.803-806 (Non-Patent Document 1). Regarding the phase change ofchalcogenide materials, there is a description in Journal of AppliedPhysics, Volume 87, Issue 9, May 2000, p. 4130 (Non-Patent Document 2).

Moreover, Japanese Patent Application Laid-Open Publication No.2003-174144 (Patent Document 1), U.S. Patent Application Publication No.US 2004/0026731 (Patent Document 2), and U.S. Patent ApplicationPublication No. US 2003/0047727 (Patent Document 3) describe techniquesfor inserting an adhesive layer between an electrode and a chalcogenidematerial layer for preventing exfoliation between the electrode and thechalcogenide material layer in a phase-change memory.

In addition, as a result of prior art document research carried out bythe inventor of the present invention, Japanese Patent ApplicationLaid-Open Publication No. 2004-288843 (Patent Document 4) describes astructure in which a stacked film comprising an amorphous thin filmcontaining chalcogenide and a top electrode is formed so that thestacked film is connected to a bottom electrode via an opening formed inan insulating film on the bottom electrode formed on a siliconsubstrate.

Patent Document 1: Japanese Patent Application Laid-Open Publication No.2003-174144

Patent Document 2: U.S. Patent Application Publication No. US2004/0026731

Patent Document 3: U.S. Patent Application Publication No. US2003/0047727

Patent Document 4: Japanese Patent Application Laid-Open Publication No.2004-288843

Non-Patent Document 1: Technical Digest of International Electron DeviceMeeting, 2001, p. 803-806

Non-Patent Document 2: Journal of Applied Physics, Volume 87, Issue 9,May 2000, p. 4130

DISCLOSURE OF THE INVENTION

The inventor of the present invention has studied semiconductor deviceshaving phase-change memories formed by using chalcogenide materials, andas a result, the following points have been elucidated. Specifically,the inventor of the present invention has found out that there is aproblematic point that, since a chalcogenide material has lowadhesiveness, it is readily exfoliated from an interlayer dielectricfilm formed of a silicon oxide film formed on a semiconductor substratein a manufacturing process of a phase-change memory.

Hereinafter, the semiconductor devices having the phase-change memorycells studied by the inventor of the present invention will be describedwith reference to FIG. 7 to FIG. 11. FIG. 7 to FIG. 9 are crosssectional views of main parts schematically showing an example of thesemiconductor devices in manufacturing steps studied by the inventor ofthe present invention, and FIG. 10 and FIG. 11 are cross sectional viewsof main parts schematically showing examples of the semiconductordevices studied by the inventor of the present invention. Note that, inFIG. 7 to FIG. 11, phase change memories are shown as a main part of thesemiconductor devices.

An example of a manufacturing process of a phase-change memory cell willbe briefly described with reference to FIG. 7 to FIG. 9. As shown inFIG. 7, after a select transistor comprising, for example, a MOStransistor and a bipolar transistor is formed by a known manufacturingmethod on a semiconductor substrate not shown, an interlayer dielectricfilm 1 formed of, for example, a silicon oxide film is deposited on theselect transistor by a known manufacturing method. Then, a plug 2 formedof, for example, tungsten is formed in the interlayer dielectric film 1.This plug functions to electrically connect the select transistor belowand a chalcogenide material layer (phase-change material layer) above toeach other. Next, a chalcogenide material layer 3 formed of, forexample, GeSbTe, a top electrode 4 formed of, for example, tungsten, anda hard mask 5 formed of, for example, a silicon oxide film aresequentially deposited.

Subsequently, as shown in FIG. 8, the hard mask 5, the top electrode 4,and the chalcogenide material layer 3 are sequentially processed by aknown lithography method and dry etching method.

Subsequently, as shown in FIG. 9, an interlayer dielectric film 6 isdeposited so as to cover the processed hard mask 5, top electrode 4, andchalcogenide material layer 3. Then, a wiring layer which iselectrically connected to the top electrode 4 is formed above theinterlayer dielectric film 6, and a plurality of wiring layers arefurther formed thereabove (not shown). The phase-change memory cell issubstantially completed by the above steps.

Meanwhile, in the structure of such a phase-change memory cell, theadhesiveness of the chalcogenide material layer 3 is low; therefore,there arises the problem that exfoliation from the interlayer dielectricfilm 1 formed of a silicon oxide film formed on the semiconductorsubstrate in the manufacturing process of the phase-change memoryreadily occurs.

Accordingly, the inventor of the present invention has carried out astudy for preventing exfoliation of the chalcogenide material layer fromthe interlayer dielectric film formed of a silicon oxide film formed onthe semiconductor substrate in the manufacturing process of thephase-change memory. Herein, the interlayer dielectric film uses asilicon oxide film formed by a chemical vapor deposition method (CVDmethod), for example, a so-called P-TEOS film formed by a plasma CVDmethod using tetraethoxysilane (Si(OC₂H₅)₄):TEOS) and oxygen as its rawmaterials is used.

The phase-change memory shown in FIG. 10 is formed on a main surface ofa semiconductor substrate (not shown) and has a structure in which anadhesive layer 7 formed of a conductive material such as Ti is formed ona plug 2 and an interlayer dielectric film 1, and a chalcogenidematerial layer 3 is formed on the adhesive layer 7. Since the adhesivelayer 7 is provided on the entire surface of the interface between thechalcogenide material layer 3 and the interlayer dielectric film 1 inthis manner, exfoliation of the chalcogenide material layer 3 can beprevented. However, in this structure, when a voltage is applied fromthe plug 2 in a rewrite operation of the phase-change memory, a currentmainly flows in the lateral direction of the adhesive layer 7 (directionparallel to the substrate surface) since the adhesive layer 7 has alower resistivity than the chalcogenide material layer 3. In this case,the region of the chalcogenide material layer that is heated by Jouleheat is expanded to the entire surface of the part that is in contactwith the adhesive layer 7; therefore, there arises a problem that anextremely large current is required for crystallization or amorphizationof the chalcogenide material layer.

The above-mentioned problem can be solved by forming the adhesive layer7 formed of a conductive material only in a region that is not incontact with the plug 2 as shown in FIG. 11. In this case, the region ofthe chalcogenide material layer 3 that is heated by Joule heat islimited to a part that is in contact with the plug 2; therefore, thecurrent required for crystallization or amorphization of thechalcogenide material layer 3 is reduced compared with the case of FIG.10. However, since the region in which the adhesive layer is notprovided exists at the interface between the chalcogenide material layer3 and the interlayer dielectric film 1, the exfoliation of thechalcogenide material layer cannot be completely prevented. Moreover,after the conductive material is formed on the entire surface of thesubstrate including the interlayer dielectric film 1 and the plug 2, astep of removing the conductive material except for that of the adhesivelayer 7 on the plug 2 is additionally required. In this case, therearise problems that the number of masks is increased, thereby increasingthe manufacturing cost and that the alignment margin is reduced whenmemory cells are miniaturized, thereby reducing yield and reliability.

In the above-described Patent Documents 1 to 4 and Non-Patent Documents1 to 2, there are not described techniques for solving these problems ofincrease of current for crystallization or amorphization of thechalcogenide material layer, increase of the manufacturing cost, andreduction of yield and reliability; and thus a technique capable ofpreventing exfoliation of the chalcogenide material layer withoutadversely affecting the rewrite property of the phase-change memory isdesired.

It is an object of the present invention to provide a technique capableof preventing a chalcogenide material layer on an interlayer dielectricfilm from exfoliating from the interlayer dielectric film withoutproviding an adhesive layer on the lower surface of the chalcogenidematerial layer.

The above and other objects and novel characteristics of the presentinvention will be apparent from the description of this specificationand the accompanying drawings.

The effects obtained by typical aspects of the present invention will bebriefly described below.

The present invention is a method of manufacturing a semiconductordevice comprising: an interlayer dielectric film formed on a mainsurface of a semiconductor substrate; a chalcogenide material layerprovided so as to extend on the interlayer dielectric film; and a topelectrode provided on the chalcogenide material layer, where theinterlayer dielectric film is formed containing at least silicon,oxygen, and fluorine.

Further, it is a method of manufacturing a semiconductor devicecomprising: an interlayer dielectric film formed on a main surface of asemiconductor substrate; a chalcogenide material layer provided so as toextend on the interlayer dielectric film; and a top electrode providedon the chalcogenide material layer, where at least fluorine is adsorbedonto the interlayer dielectric film and the plug.

Moreover, the present invention is a semiconductor device comprising: aninterlayer dielectric film formed on a main surface of a semiconductorsubstrate; a chalcogenide material layer provided so as to extend on theinterlayer dielectric film; and a top electrode provided on thechalcogenide material layer, where a fluorine concentration in aninterface between the interlayer dielectric film and the chalcogenidematerial layer is higher than a fluorine concentration in an interfacebetween the chalcogenide material layer and the top electrode.

The effects obtained by typical aspects of the present invention will bebriefly described below.

According to the present invention, exfoliation from the interlayerdielectric film can be prevented.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a cross sectional view of main parts schematically showing aphase-change memory cell according to the present invention;

FIG. 2 is an explanatory diagram showing current pulse specificationsfor changing phase states of chalcogenide;

FIG. 3 is a cross sectional view of main parts schematically showing asemiconductor device according to a first embodiment;

FIG. 4 is an explanatory diagram showing a fluorine concentrationdistribution in interlayer dielectric films of FIG. 3;

FIG. 5 is a cross sectional view of main parts schematically showing asemiconductor device according to a second embodiment;

FIG. 6 is an explanatory diagram showing a fluorine concentrationdistribution in interlayer dielectric films of FIG. 5;

FIG. 7 is a cross sectional view of main parts schematically showing afirst example of semiconductor devices in a manufacturing step studiedby the inventor of the present invention;

FIG. 8 is a cross sectional view of main parts schematically showing thesemiconductor device in a manufacturing step continued from FIG. 7;

FIG. 9 is a cross sectional view of main parts schematically showing thesemiconductor device in a manufacturing step continued from FIG. 8;

FIG. 10 is a cross sectional view of main parts schematically showing asecond example of the semiconductor devices studied by the inventor ofthe present invention; and

FIG. 11 is a cross sectional view of main parts schematically showing athird example of the semiconductor devices studied by the inventor ofthe present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. Note that,components having the same function are denoted by the same referencesymbols throughout the drawings for describing the embodiment, and therepetitive description thereof will be omitted.

FIRST EMBODIMENT

First, a phase-change memory cell according to the present inventionwill be described with reference to FIG. 1 and FIG. 2. FIG. 1 is a crosssectional view of main parts schematically showing the phase-changememory cell according to the present invention. FIG. 2 is an explanatorydiagram showing current pulse specifications for changing phase statesof a chalcogenide.

The phase-change memory of FIG. 1 comprises: an interlayer dielectricfilm 8 provided above a select transistor (not illustrated) formed on amain surface of a semiconductor substrate; a plug 2 selectively providedpenetrating through the interlayer dielectric film 8 and having an endelectrically connected to the select transistor; a chalcogenide materiallayer 3 electrically connected to the other end of the plug 2 andprovided so as to extend on the interlayer dielectric film 8; and a topelectrode 4 provided on the chalcogenide material layer 3. Note that,although it will be described later, a fluorine concentration in aninterface between the interlayer dielectric film 8 and the chalcogenidematerial layer 3 is higher than a fluorine concentration in an interfacebetween the chalcogenide material layer 3 and the top electrode 4.

A feature of such a phase-change memory resides in that a read signal islarge since the resistance value of the chalcogenide material is changedby 2 to 3 digits in accordance with the crystalline state and theresistance value is used as the signal. As a result, sensing operationis facilitated, and the speed of reading is increased. In addition tothis, it has a performance that compensates for the drawback of FLASHmemory, for example, rewrite can be performed for 10¹² times. Moreover,features such as that operation can be performed with a low voltage andlow power and that mixed embedding with a logic circuit is easy aresuitable for mobile devices.

Here, operation principles of the phase-change memory will be describedwith FIG. 2. When the chalcogenide material is to be amorphized, a resetpulse that heats the temperature of the chalcogenide material to amelting point or above and then cools it rapidly is applied. The meltingpoint is, for example, about 600° C. The time for rapid cooling (t1) is,for example, about 2 nsec. When the chalcogenide material is to becrystallized, a set pulse that keeps the temperature of the chalcogenidematerial to a temperature that is higher than or equal to acrystallization temperature and lower than or equal to the melting pointis applied. The crystallization temperature is, for example, about 400°C. The time required for crystallization (t2) is, for example, about 50nsec.

The phase change memory according to the present invention shown in FIG.1 is not provided with the adhesive layer 7 which comprises a conductivematerial such as Ti or Al as shown in above-described FIG. 10 and FIG.11. The above-described adhesive layer 7 is provided to enhance thebonding force of the interface because the conductive material isreadily reacted with the chalcogenide material so that the exfoliationresistance of the chalcogenide material layer 3 is improved. However, asmentioned above, there arise the problems that, for example, a largecurrent is required for carrying out phase change and that an additionalstep is required.

Accordingly, in the phase-change memory according to the present firstembodiment, the adhesive layer comprising a conductive material is notprovided, and the interlayer dielectric film 8 is caused to containfluorine to improve the exfoliation resistance of the chalcogenidematerial layer so as to chemically bond the fluorine and thechalcogenide material to each other, thereby increasing the adhesionforce between the interlayer dielectric film 8 and the chalcogenidematerial layer 3. Therefore, other than the conductive material,exfoliation of the chalcogenide material layer can be prevented also byusing an insulating material containing fluorine. This is for the reasonthat fluorine chemically reacts with both the insulating material andchalcogenide material to increase the bonding force.

As described above, in the phase-change memory cell according to thepresent invention, since the interlayer dielectric film 8 containsfluorine, the fluorine concentration in the interface between theinterlayer dielectric film 8 and the chalcogenide material layer 3 ishigher than the fluorine concentration in the interface between thechalcogenide material layer 3 and the top electrode 4.

Here, an example of a manufacturing process will be described withreference to FIG. 1. First, the select transistor is formed on thesemiconductor substrate not shown by a known manufacturing method. Then,the interlayer dielectric film 8 formed of, for example, a silicon oxidefilm containing fluorine (e.g., SiOF film) is deposited, and the plug 2formed of, for example, tungsten is formed in the interlayer dielectricfilm 8. Then, the chalcogenide material layer 3 formed of, for example,GeSbTe, the top electrode 4 formed of, for example, tungsten, and thehard mask 5 formed of, for example, a silicon oxide film aresequentially deposited. Then, the hard mask 5, the top electrode 4, andthe chalcogenide material layer 3 are processed by a known lithographymethod and dry etching method. Finally, by depositing the interlayerdielectric film 6, the state as shown in FIG. 1 is achieved.

As described above, the above-described interlayer dielectric film 1 ofFIG. 10 and FIG. 11 comprises, for example, a so-called P-TEOS filmformed by a plasma CVD method using tetraethoxysilane (Si(OC₂H₅)₄: TEOS)and oxygen as its raw materials. In the first embodiment, in formationof the interlayer dielectric film 8 containing fluorine, one of gasmaterials containing fluorine is fed during formation of the P-TEOSfilm. The gas containing fluorine is a gas comprising at least one ormore kinds of gases selected from, for example, F₂, CF₄, C₂F₆, CHF₃,CH₂F₂, C₃F₈, C₄F₈, SF₆, SiF₄, and NF₃. Consequently, the interlayerdielectric film 8 that is excellent in the adhesiveness to thechalcogenide material layer and contains at least silicon, oxygen, andfluorine can be formed.

Here, regarding the concentration of fluorine in the interlayerdielectric film 8 of the first embodiment, the concentration of fluorinein the interface with the chalcogenide material layer 3 is required tobe 0.1 at. % or more with respect to silicon. In addition, since onlythe vicinity of the interface with the chalcogenide material layer 3contributes to prevent exfoliation of the chalcogenide material layer 3,the fluorine concentration in the upper surface of the interlayerdielectric film 8 is desired to be higher than the fluorineconcentration in the lower surface. Note that, as the element containedin the interlayer dielectric film 8, chlorine, bromine, or iodine ofhalogen family can also obtain similar effects other than fluorine.

Note that, as a result of the prior art document research made by theinventor of the present invention, in Japanese Patent ApplicationLaid-Open Publication No. 2004-288843 (Patent Document 4), SiOF ismentioned as an example of an insulating film material formed under achalcogenide material layer; however, the adhesiveness with thechalcogenide material layer is not clearly mentioned. Therefore, in theabove-mentioned Patent Document 4, insulating materials such as SiO₂ andSi₃N₄ having bad adhesiveness with the chalcogenide material are alsomentioned as examples of the insulating film material formed under thechalcogenide material layer. Thus, it is different from the presentinvention where the fact has been found out that, when the interlayerdielectric film containing fluorine is used, exfoliation of thechalcogenide material layer can be prevented without using an adhesivelayer because the fluorine and chalcogenide material are chemicallybonded to each other to increase the adhesion force.

According to this means of the first embodiment, since the interlayerdielectric film 8 containing fluorine is formed on the lower surface ofthe chalcogenide material layer 3, the adhesion force of thechalcogenide material layer 3 is enhanced, and exfoliation during themanufacturing process can be prevented. In addition, since an adhesivelayer is not required to be newly added, exfoliation of the chalcogenidematerial layer 3 can be prevented without exerting adverse effects onthe rewrite property of the phase-change memory.

Next, a semiconductor device using a phase-change memory cell accordingto the present invention will be described with reference to FIG. 3 andFIG. 4. FIG. 3 is a cross sectional view of main parts schematicallyshowing the semiconductor device according to the first embodiment. FIG.4 is an explanatory diagram showing a fluorine concentrationdistribution in interlayer dielectric films of FIG. 3.

The semiconductor device of FIG. 3 is an example specifically showing ameans of forming the interlayer dielectric film containing fluorineunder a chalcogenide material layer as described above. An example of amanufacturing process of the semiconductor device according to the firstembodiment will be described with FIG. 3.

First, after a semiconductor substrate 101 is prepared, an isolationoxide film 102 for isolating a MOS transistor, which is used as theselect transistor, is formed on a surface of the semiconductor substrate101 by a known selective oxidation method or shallow trench isolationmethod. In the first embodiment, to form the isolation oxide film 102,for example, the shallow trench isolation method capable of planarizingthe surface is used. Specifically, isolation trenches are formed in thesemiconductor substrate 101 by using a known dry etching method anddamages caused by dry etching on the sidewalls and bottom surfaces ofthe trenches are removed, and an oxide film is then deposited by using aknown CVD method and the oxide film that is present in the part otherthan the trenches is selectively polished also by a known CMP method, sothat only the isolation oxide film 102 embedded in the trenches is left.

Subsequently, the MOS transistor used as the select transistor is formedon a main surface of the semiconductor substrate 101. Next, although itis not shown, wells of two mutually different conduction types areformed by high-energy impurity implantation. Next, after the surface ofthe semiconductor substrate 101 is cleaned, a gate oxide film 103 of theMOS transistor is formed by a known thermal oxidation method.

Subsequently, on a surface of the gate oxide film 103, a gate electrode104 formed of polycrystalline silicon and a silicon nitride film 105 aredeposited. Then, after the gate is processed by a lithography step and adry etching step, an impurity is subjected to implantation by using aresist and the gate electrode 104 as a mask, thereby forming a diffusionlayer 106. In the first embodiment, a polycrystalline polysilicon gateis used as the gate electrode 104; however, as a low-resistance gate, apolymetal gate having a laminated structure of metal/barriermetal/polycrystalline silicon can be also used.

Subsequently, a silicon nitride film 107 is deposited by a CVD methodfor self align contact application. Then, an interlayer dielectric film108 comprising a silicon oxide film is deposited on the entire surface,and it is subjected to planarization of surface unevenness caused by thegate electrode 104 by using a known CMP method.

Subsequently, by a lithography step and a dry etching step, plug contactholes are opened in the interlayer dielectric film 108. In this process,to avoid exposure of the gate electrode 104, the interlayer dielectricfilm 108 is processed under the conditions of so-called self alignment,in other words, under the conditions that the silicon oxide film ishighly selected with respect to the silicon nitride film.

Note that the steps below can be also used as a measure for misalignmentof the plug contact holes with respect to the diffusion layer 106.Specifically, there is also a step usable in which, the interlayerdielectric film 108 is subjected to dry etching under the conditionsthat the silicon oxide film is highly selected with respect to thesilicon nitride film so that the silicon nitride film on the uppersurface of the diffusion layer 106 is left, and then dry etching iscarried out under the conditions that the silicon nitride film is highlyselected with respect to the silicon oxide film so that the siliconnitride film on the upper surface of the diffusion layer 106 is removed.

Subsequently, tungsten is buried in the plug contact holes, and tungstenplugs 109 are formed by a known CMP method. Next, tungsten having a filmthickness of, for example, about 100 nm is deposited by a sputteringmethod, and the tungsten is processed by a lithography step and a dryetching step, thereby forming a first wiring layer 110.

Subsequently, an interlayer dielectric film 119 comprising a siliconoxide film (for example, SiOF film) containing fluorine is deposited byusing a plasma CVD method using TEOS, O₂, and F₂ as raw materials andsubjected to planarization of surface unevenness caused by the firstwiring layer by using a known CMP method. In the first embodiment, thesilicon oxide film containing fluorine is formed as the interlayerdielectric film 119 containing fluorine by using the plasma CVD methodusing TEOS, O₂, and F₂ as raw materials; however, the film is notlimited thereto, and an interlayer dielectric film having a siliconoxide film as a base material can be formed by a chemical vapordeposition method using, for example, CF₄, C₂F₆, CHF₃, CH₂F₂, C₃F₈,C₄F₈, SF₆, SiF₄, and NF₃ as one of raw materials.

Subsequently, a plug contact hole is opened in the interlayer dielectricfilm 119 by a lithography step and a dry etching step. Then, tungsten isburied in the plug contact hole, and a tungsten plug 112 is formed by aknown CMP method.

Subsequently, a chalcogenide material layer 113 comprising GeSbTe havinga film thickness of, for example, about 100 nm and a top electrode 114formed of tungsten having a film thickness of, for example, about 50 nmare sequentially deposited by a known sputtering method. In the firstembodiment, GeSbTe is used as the chalcogenide material layer 3;however, the material is not limited to this, and a chalcogenidematerial containing at least two or more elements selected from Ge, Sb,and Te can be used. Also, a chalcogenide material containing at leasttwo or more elements selected from Ge, Sb, and Te and at least oneelement selected from the group 1b, the group 2b, and the groups 3a to7a of the periodic table may be used.

Subsequently, a silicon oxide film 115 is deposited by a known CVDmethod. Then, the silicon oxide film 115, the top electrode 114, and thechalcogenide material layer 113 are sequentially processed by a knownlithography step and dry etching step.

Subsequently, an interlayer dielectric film 116 comprising a siliconoxide film is deposited on the entire surface and subjected toplanarization of surface unevenness by using a known CMP method. Then, aplug contact hole is opened in the interlayer dielectric film 116 andthe silicon oxide film 115 by a lithography step and a dry etching step.Then, tungsten is buried in the plug contact hole, and a tungsten plug117 is formed by a known CMP method.

Subsequently, aluminum having a film thickness of 200 nm is deposited,and it is processed as a wiring layer so as to form a second wiringlayer 118. As a matter of course, copper having low resistance can beused instead of aluminum. The semiconductor device having thephase-change memory cell of the first embodiment shown in FIG. 3 issubstantially completed by the above-described steps.

According to the first embodiment, since the interlayer dielectric filmcontaining fluorine is formed on the lower surface of the chalcogenidematerial layer, the adhesion force of the chalcogenide material layer isincreased, thereby increasing exfoliation during manufacturing steps.

A desired fluorine concentration distribution in respective interlayerdielectric films in the semiconductor device according to the firstembodiment is shown in FIG. 4. This fluorine concentration distributionis corresponding to a result of carrying out an elemental analysis inthe depth direction in the order of the interlayer dielectric films 116,119, and 108 of FIG. 3. The horizontal axis represents the depth in thefilm thickness direction, and the vertical axis represents the relativeconcentration of fluorine.

As shown in FIG. 4, only the interlayer dielectric film 119 positionedunder the chalcogenide material layer is required to form the interlayerdielectric film containing fluorine; therefore, the fluorineconcentration thereof is relatively high compared with the interlayerdielectric films 116 and 108. Fluorine may be added to the interlayerdielectric film 116 and the interlayer dielectric film 108; however,since mechanical strength is reduced when the fluorine concentration inthe silicon oxide film is high, it is desired that fluorine is notintentionally added to the interlayer dielectric films that do notcontribute to adhesion force improvement of the chalcogenide materiallayer. For the reason similar to this, also about the interlayerdielectric film 119, the fluorine concentration in the upper surface ofthe interlayer dielectric film 119 is desired to be higher than thefluorine concentration in the lower surface because the part except forthe vicinity of the interface with the chalcogenide material layer doesnot contribute to adhesion improvement. For example, when the gascontaining fluorine is fed as one of raw materials during formation ofthe interlayer dielectric film, the gas flow rate can be increased in afilm formation latter stage compared with that in a film formationinitial stage. As a result, the fluorine concentration distribution inthe interlayer dielectric film 119 has the state as shown in FIG. 4.

In this manner, in the semiconductor device according to the firstembodiment, the chalcogenide material layer 113 on the interlayerdielectric film 119 can be prevented from exfoliating from theinterlayer dielectric film 119 without providing an adhesive layer onthe lower surface of the chalcogenide material layer 113.

SECOND EMBODIMENT

In the above-described first embodiment, the case in which theinterlayer dielectric film containing fluorine is formed below thechalcogenide material layer has been described; however, in a presentsecond embodiment, the case in which fluorine is added to the interfacebetween the chalcogenide material layer and the interlayer dielectricfilm will be described.

As described above, in the phase-change memory according to the presentinvention shown in FIG. 1, the adhesive layer 7 formed of a conductivematerial such as Ti or Al is not provided like shown in above-describedFIG. 10 and FIG. 11. The above-described adhesive layer 7 is providedsince the conductive materials are readily reacted with the chalcogenidematerial, the bonding force of the interface is enhanced, and theexfoliation resistance of the chalcogenide material layer 3 is improved.However, as described above, the problems such that a large current isrequired for phase change and that the additional step is required aregenerated.

Accordingly, in a phase change memory according to the secondembodiment, instead of providing the adhesive layer formed of aconductive material, fluorine is added to the interface between thechalcogenide material layer 3 and the interlayer dielectric film 8 so asto improve the exfoliation resistance of the chalcogenide materiallayer, thereby causing the fluorine and the chalcogenide material to bechemically bonded to each other to increase the adhesion force betweenthe interlayer dielectric film 8 and the chalcogenide material layer 3.In other words, other than the conductive material, exfoliation of thechalcogenide material layer 3 can be prevented also by adding fluorineto the interface between the chalcogenide material layer 3 and theinterlayer dielectric film 8. This is because that fluorine ischemically reacted with both the insulating material and thechalcogenide material and functions to increase the adhesion force.

As described above, in the phase-change memory cell according to thepresent invention, when fluorine is added to the interface between thechalcogenide material layer 3 and the interlayer dielectric film 8, thefluorine concentration in the interface between the interlayerdielectric film 8 and the chalcogenide material layer 3 becomes higherthan the fluorine concentration in the interface between thechalcogenide material layer 3 and the top electrode 4.

Here, an example of a manufacturing process will be described withreference to FIG. 1. First, a select transistor is formed on asemiconductor substrate not shown by a known manufacturing method. Next,by using a known manufacturing method, the interlayer dielectric film 8comprising, for example, a silicon oxide film is deposited, and the plug2 formed of, for example, tungsten is formed in the interlayerdielectric film 8. Then, a gas containing fluorine is caused to flow,and fluorine is absorbed onto the interlayer dielectric film 8 and theplug 2. Then, the chalcogenide material layer 3 formed of, for example,GeSbTe, the top electrode 4 formed of, for example, tungsten, and thehard mask 5 comprising, for example, a silicon oxide film aresequentially deposited. Then, the hard mask 5, the top electrode 4, andthe chalcogenide material layer 3 are processed by a known lithographymethod and dry etching method. Then, when the interlayer dielectric film6 is deposited, the state as shown in FIG. 1 is achieved. Examples ofthe gas caused to flow for adsorbing the fluorine include F₂, CF₄, C₂F₆,CHF₃, CH₂F₂, C₃F₈, C₄F₈, SF₆, SiF₄, and NF₃.

Here, the fluorine concentration in the interface between thechalcogenide material layer 3 and the interlayer dielectric film 8 ofthe second embodiment is required to be 0.1 at. % or more with respectto silicon. Only the vicinity of the interface with the interlayerdielectric film 8 contributes to exfoliation prevention of thechalcogenide material layer 3; therefore, the fluorine concentration inthe interface between the chalcogenide material layer 3 and theinterlayer dielectric film 8 is desired to be higher than the fluorineconcentration in the interface between the chalcogenide material layer 3and the top electrode 4. Note that, as the element to be added to theinterface between the chalcogenide material layer 3 and the interlayerdielectric film 8, not only fluorine but also chlorine, bromine, oriodine of the halogen family can obtain similar effects.

According to this means of the second embodiment, fluorine is added tothe interface between the chalcogenide material layer 3 and theinterlayer dielectric film 8; therefore, the adhesion force of thechalcogenide material layer 3 is enhanced, and exfoliation duringmanufacturing process can be prevented. Moreover, since an adhesivelayer is not required to be newly added, exfoliation of the chalcogenidematerial layer 3 can be prevented without exerting adverse effects onthe rewrite property of the phase-change memory.

Next, a semiconductor device using the phase-change memory according tothe present invention will be described with reference to FIG. 5 andFIG. 6. FIG. 5 is a cross sectional view of main parts schematicallyshowing the semiconductor device according to the second embodiment.FIG. 6 is an explanatory diagram showing a fluorine concentrationdistribution in interlayer dielectric films of FIG. 5.

The semiconductor device of FIG. 5 is an example specifically showingthe means of adding fluorine to the interface between the chalcogenidematerial layer and the interlayer dielectric film as described above. Anexample of a manufacturing process of the semiconductor device accordingto the second embodiment will be described with FIG. 5. Note that, thesteps are same as those of the above-described first embodiment up tothe step of forming the tungsten plug 109; therefore, the descriptionthereof is omitted.

After the tungsten plug 109 is formed, tungsten having a film thicknessof, for example, about 100 nm is deposited by a sputtering method on theinterlayer dielectric film 108 and the tungsten plug 109, and thetungsten is processed by a lithography step and a dry etching step,thereby forming the first wiring layer 110.

Subsequently, an interlayer dielectric film 111 comprising a siliconoxide film is deposited by using a plasma CVD method using TEOS and O₂as raw materials, and this is subjected to planarization of surfaceunevenness caused by the first wiring layer by using a known CMP method.Then, after a plug contact hole is opened by a lithography step and adry etching step, tungsten is buried in the plug contact hole, and thetungsten plug 112 is formed by a known CMP method.

Subsequently, for example, a F₂ gas is caused to flow, and fluorine isadsorbed onto the interlayer dielectric film 111 and the tungsten plug112. Note that, in the second embodiment, F₂ is used as the gas foradsorbing fluorine; however, the gas is not limited to this, and, forexample, CF₄, C₂F₆, CHF₃, CH₂F₂, C₃F₈, C₄F₈, SF₆, SiF₄, and NF₃ can beused. As a matter of course, if the above-described gas is fed inplasma, adsorption of fluorine to the surface of the interlayerdielectric film 111 becomes more significant; therefore, this isdesirable for improving the adhesion force of the chalcogenide materiallayer 113.

Subsequently, the chalcogenide material layer 113 formed of GeSbTehaving a film thickness of, for example, about 100 nm and the topelectrode 114 formed of tungsten having a film thickness of, forexample, about 50 nm are sequentially deposited by a known sputteringmethod. Note that, in the second embodiment, GeSbTe is used as thechalcogenide material layer 113; however, the material is not limited tothis, and a chalcogenide material containing at least two or moreelements selected from Ge, Sb, and Te can be used. Also, a chalcogenidematerial containing at least two or more elements selected from Ge, Sb,and Te and at least one element selected from the elements of the group1b, the group 2b, and the groups 3a to 7a of the periodic table may beused.

Subsequently, the silicon oxide film 115 is deposited by a known CVDmethod. Then, the silicon oxide film 115, the top electrode 114, and thechalcogenide material layer 113 are sequentially processed by a knownlithography step and dry etching step.

The steps thereafter are same as those of the first embodiment;therefore, the descriptions thereof will be omitted. The phase-changememory cell of the present embodiment shown in FIG. 5 is substantiallycompleted by the above steps.

In the semiconductor device according to the second embodiment, fluorineis added to the interface between the chalcogenide material layer 113and the interlayer dielectric film 111; thus, the adhesion force of thechalcogenide material layer 113 is enhanced. Therefore, the chalcogenidematerial layer 113 on the interlayer dielectric film 111 can beprevented from exfoliating from the interlayer dielectric film 111without providing an adhesive layer on the lower surface of thechalcogenide material layer 113.

A desired fluorine concentration distribution in the interlayerdielectric films in the semiconductor device according to the secondembodiment is shown in FIG. 6. This fluorine concentration distributioncorresponds to a result of carrying out elemental analysis in the depthdirection in the order of the interlayer dielectric films 116, 111, and108 of FIG. 5. The horizontal axis represents the depth in the filmthickness direction, and the vertical axis represents the relativeconcentration of fluorine.

As shown in FIG. 6, since fluorine is added to the interface between thechalcogenide material layer 113 and the interlayer dielectric film 111,the fluorine concentration of the interface between the interlayerdielectric film 116 and the interlayer dielectric film 111 is high.Fluorine may be added into the films of the interlayer dielectric film116, the interlayer dielectric film 111, and the interlayer dielectricfilm 108; however, since the mechanical strength is reduced when thefluorine concentration in the silicon oxide film is increased, it isdesired that fluorine is not intentionally added to the regions that donot contribute to adhesion force improvement of the chalcogenidematerial layer.

As described above, in the semiconductor device according to the secondembodiment, the chalcogenide material layer 113 on the interlayerdielectric film 111 can be prevented from exfoliating from theinterlayer dielectric film 111 without providing an adhesive layer onthe lower surface of the chalcogenide material layer 113.

In the foregoing, the invention made by the inventor of the presentinvention has been concretely described based on the embodiments.However, it is needless to say that the present invention is not limitedto the foregoing embodiments and various modifications and alterationscan be made within the scope of the present invention.

For example, in the above-described embodiments, the case in which thechalcogenide material formed of GeSbTe is applied to the chalcogenidematerial layer has been described; however, they are also applicable toa chalcogenide material containing Ge which is readily chemicallyreacted with fluorine.

According to the invention disclosed in the present specification,exfoliation from the interlayer dielectric film can be prevented.Consequently, ununiformity of electric characteristics and deteriorationof reliability caused by the manufacturing process of the phase-changememory can be suppressed, and furthermore, the current for rewrite canbe reduced to a level at which a MOS transistor can be operated byenhancing the efficiency of heat generation.

INDUSTRIAL APPLICABILITY

The present invention can be widely utilized in the manufacturingindustry of manufacturing a semiconductor device having a phase-changememory cell formed of a chalcogenide material.

1. A method of manufacturing a semiconductor device comprising the stepsof: (a) forming a select transistor on a main surface of a semiconductorsubstrate; (b) forming an interlayer dielectric film on the selecttransistor; (c) forming a plug having an end electrically connected tothe select transistor in the interlayer dielectric film; (d) forming achalcogenide material layer electrically connected to the other end ofthe plug on the interlayer dielectric film and the plug; and (e) forminga top electrode on the chalcogenide material layer, wherein, in the step(b), the interlayer dielectric film is formed containing at leastsilicon, oxygen, and fluorine.
 2. The method of manufacturing asemiconductor device according to claim 1, wherein, in the step (b), theinterlayer dielectric film is formed by a chemical vapor depositionmethod using a gas containing at least fluorine as one of raw materials.3. The method of manufacturing a semiconductor device according to claim2, wherein the gas containing fluorine comprises at least one or moregases selected from F₂, CF₄, C₂F₆, CHF₃, CH₂F₂, C₃F₈, C₄F₈, SF₆, SiF₄,and NF₃.
 4. A method of manufacturing a semiconductor device comprisingthe steps of: (a) forming a select transistor on a main surface of asemiconductor substrate; (b) forming an interlayer dielectric film onthe select transistor; (c) forming a plug having an end electricallyconnected to the select transistor in the interlayer dielectric film;(d) forming a chalcogenide material layer electrically connected to theother end of the plug on the interlayer dielectric film and the plug;and (e) forming a top electrode on the chalcogenide material layer,wherein, between the step (c) and the step (d), a step of (f) causing agas containing at least fluorine to be adsorbed onto the interlayerdielectric film and the plug is comprised.
 5. The method ofmanufacturing a semiconductor device according to claim 4, wherein thegas containing fluorine comprises at least one or more gases selectedfrom F₂, CF₄, C₂F₆, CHF₃, CH₂F₂, C₃F₈, C₄F₈, SF₆, SiF₄, and NF₃.
 6. Asemiconductor device comprising: a semiconductor substrate; a selecttransistor formed on a main surface of the semiconductor substrate; aninterlayer dielectric film provided above the select transistor; a plugselectively provided so as to penetrate through the interlayerdielectric film and having an end electrically connected to the selecttransistor; a chalcogenide material layer electrically connected to theother end of the plug and provided so as to extend on the interlayerdielectric film; and a top electrode provided on the chalcogenidematerial layer, wherein a fluorine concentration in an interface betweenthe interlayer dielectric film and the chalcogenide material layer ishigher than a fluorine concentration in an interface between thechalcogenide material layer and the top electrode.
 7. The semiconductordevice according to claim 6, wherein the interlayer dielectric filmcomprises a material containing at least silicon, oxygen, and fluorine.8. The semiconductor device according to claim 6, wherein fluorine isadded to the interface between the interlayer dielectric film and thechalcogenide material layer.
 9. The semiconductor device according toclaim 6, wherein the fluorine concentration in an upper surface of theinterlayer dielectric film is higher than the fluorine concentration ina lower surface of the interlayer dielectric film.
 10. The semiconductordevice according to claim 6, wherein the chalcogenide material layer isin direct contact with the interlayer dielectric film.
 11. Thesemiconductor device according to claim 6, wherein the chalcogenidematerial layer is in direct contact with the plug.